Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 (which is incorporated herein by reference for all purposes) discloses a split gate non-volatile memory cell. FIG. 1 illustrates an example of such a split gate memory cell formed on a semiconductor substrate 12. Source and drain regions 16 and 14 are formed as diffusion regions in substrate 12, and define a channel region 18 therebetween. The memory cell includes four conductive gates: a floating gate 22 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 16, a control gate 26 disposed over and insulated from the floating gate 22, an erase gate 24 disposed over and insulated from the source region 16, and a select gate 20 disposed over and insulated from a second portion of the channel region 18. A conductive contact 10 can be formed to electrically connect to the drain region 14.
The memory cells are arranged in an array, with columns of such memory cells separated by columns of isolation regions. Isolation regions are portions of the substrate in which insulation material is formed. Logic (core) devices and high voltage devices can be formed on the same chip as the memory array, often formed sharing some of the same processing steps. It is also known to make the memory cell gates and the gates of the logic and high voltage gates of a high K metal material (HKMG—high K dielectric underneath metal layer). However, it has been discovered that during logic device processing, the stacks of memory cell structure can be degraded.
The present invention is a technique for forming a split gate non-volatile memory device on the same chip as logic and high voltage devices with less memory cell structure degradation.